//Jeff Szcinski & KQBright
//Lab 2
//ECEN 4243
//Spring 2014

module ClkReg32 (Q, D, clk); 
	output [31:0] Q; 
	input [31:0] D; 
	input clk; 
	
	reg [31:0] Q; 
	always @(posedge clk) begin
		Q = D; 
	end 
endmodule